Keith, please define the primary role “Bus Size” plays in the A&H 96K FPGA processing. Width & Speed are both important factors in all digital processing but their function is clearly different: Size determines how much data can be transferred at one time, while Speed determines time required for the transfer.
- Is the 36 bus architecture of the SQ5 capable of efficiently managing any and all A&H’s advanced software?
- Is the stated buss differences from the SQ’s 36 up to D-Live’s 64 bus design more about input capacity than Software implementation?
- The new CQ has not released any info pursuant to it’s bus size, so a clear explanation of it’s limitations pursuant to it’s bus size would be helpful.
Keith, your ability to comprehensively explain often miss-understood processing controls (ie your clarification of “Trim Control”) is now needed to sort out the benefits and limitations of Bus Size. It is vitally important for us all to understand the precise role and limitations of the Bus count. Is the physical size difference between a 36 bus to 64 buss processing core as significant as surface controls for I/O capacity?
Hugh